Predistortion Calibration In A Transceiver Assembly

ABSTRACT

Systems and methods are provided for calibrating a digital predistorter in an integrated transceiver circuit. A digital transmitter path provides a signal from a digital input. The transmitter path includes a digital predistorter that predistorts the digital input to mitigate nonlinearities associated with a power amplifier. The integrated transceiver circuit further includes a receiver path associated with the digital transmitter path. A coupling element provides the signal from the transmitter path to the receiver path. A signal evaluator determines values for at least one parameter associated with the digital predistorter based on the signal.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit of U.S. Provisional Application No.60/441,080, which was filed Jan. 17, 2003, and entitled “Type-IIAll-Digital PLL in Deep-Submicron CMOS”, the entire contents of which isincorporated herein by reference.

TECHNICAL FIELD

The present invention is directed to communications systems and morespecifically to an integrated transceiver having predistortioncalibration.

BACKGROUND OF THE INVENTION

The use of deep-submicron CMOS processes allows for an unprecedenteddegree of integration in digital circuitry, but complicates theimplementation of traditional RF and analog circuits. For example,frequency tuning of a low-voltage deep-submicron CMOS oscillator is achallenging task due to its highly nonlinear frequency behavior withdegradation in voltage and low voltage headroom. This makes itsusceptible to the variations in the power or ground supply andsubstrate noise. A low supply voltage can negatively impact the dynamicrange of the signal and result in an increasing noise floor, thusfurther degrading the signal-to-noise ratio. At times, it is possible tofind a specific solution, such as utilizing a voltage doubler.Unfortunately, with each CMOS feature size reduction, the supply voltageneeds to be scaled down to ensure the reliability of the circuit.

The high degree of integration can lead to the generation of substantialdigital switching noise that is coupled through the power supply networkand substrate into noise sensitive analog circuits. Furthermore, theadvanced CMOS processes typically use low resistance P-substrate whichis an effective means in combating latchup problems, but exacerbatessubstrate noise coupling into the analog circuits. This problem onlygets worse with scaling down of the supply voltage.

SUMMARY OF THE INVENTION

In one aspect of the invention, an integrated transceiver circuit isprovided. A digital transmitter path provides a signal from a digitalinput. The transmitter path includes a digital predistorter thatpredistorts the digital input to mitigate nonlinearities associated witha power amplifier. The integrated transceiver circuit further includes areceiver path associated with the digital transmitter path. A couplingelement provides the signal from the transmitter path to the receiverpath. A signal evaluator determines values for at least one parameterassociated with the digital predistorter based on the signal.

In accordance with another aspect of the invention, a method is providedfor calibrating a predistortion component in a transceiver system. Afirst digital signal is provided to a transmitter path. The firstdigital signal contains amplitude information related to a desiredanalog signal. A second digital signal is provided to a transmitterpath. The second digital signal contains phase information related tothe desired analog signal. At least one of the first digital signal andthe second digital signal are predistorted in the digital domainaccording to at least one predistortion parameter. An analog signal isgenerated from the first digital signal and the second digital signal.The analog signal is processed at a receiver path associated with thetransmitter path to determine values for the at least one predistortionparameter.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other aspects of the present invention will becomeapparent to those skilled in the art to which the present inventionrelates upon reading the following description with reference to theaccompanying drawings.

FIG. 1 illustrates a transceiver system in accordance with the presentinvention.

FIG. 2 illustrates an exemplary mobile digital transceiver system inaccordance with the present invention.

FIG. 3 illustrates another exemplary mobile digital transceiver systemin accordance with the present invention.

FIG. 4 illustrates a methodology for calibrating a digital predistorterassociated with a digital transceiver.

DETAILED DESCRIPTION

The present invention is directed to an integrated transceiver circuithaving a digital predistorter. A transmitter path in the transceiverincludes a digital predistorter that distorts a digital input associatedwith a desired output of the transmitter according to one or morepredistortion parameters. For example, the predistortion can mitigatedistortion due to nonlinear behavior of a power amplifier associatedwith the transceiver. The predistorter is calibrated by providing aportion of the transmitter output to the receiver path of thetransceiver. The receiver processes and digitizes the signal andprovides the digitized signal to a digital processor for analysis. Thedigital processor determines appropriate predistortion parameters forthe predistorter. The transmitter path can also include one or morenormalization components that convert digital inputs to the transmitterfrom a normalized domain to a process-voltage-temperature(PVT)-dependent domain. The predistortion can be conducted in thenormalized domain to reduce the complexity of the predistorter.

FIG. 1 illustrates a transceiver system 10 in accordance with thepresent invention. The illustrated system comprises a digital processor12, a transmitter path 14, a receiver path 16, a power amplifier 18, andan antenna 20. The illustrated system is a time-division duplex (TDD)system that can assume a transmission mode and a receiving mode atalternating times. The system can be switched to the antenna 20 betweenthese modes via a transmit/receive (T/R) switch assembly 22 controlledby the digital processor 12. It will be appreciated that one or more ofthe digital baseband processor 12, the transmitter 14 and the receiver16 and the power amplifier 18 can be implemented as an integratedcircuit on a single deep sub-micron CMOS chip.

In the transmission mode, the digital processor 12 controls thetransmitter path 14 to provide a modulated signal to the power amplifier18. The power amplifier 18 amplifies the modulated signal and providesit to the antenna 20 for transmission. In the receiving mode, an analogsignal is received at the antenna and provided to the receiver path. Theanalog signal is processed, for example, filtered and downconverted, anddigitized on the receiver path, and a digital representation of thesignal is provided to the processor assembly.

The illustrated system can be calibrated to provide updated parametersfor the at least one predistorter. This calibration can be performedonce in the factory, each time the transceiver is powered, orperiodically during the operation of the transceiver. Duringcalibration, a signal is provided to the power amplifier 18 through thetransmission path 14 as two digital inputs. A digital phase inputcorresponding to a desired analog signal is provided to the transmitterpath 14 along a phase modulated (PM) path. The digital phase input isnormalized to the expected parameters of the system to allow the digitalprocessor 12 and other components on the phase modulated (PM) path (notshown) to operate in a normalized domain. Specifically, any phaseinformation associated with the normalized tuning word is normalized toan expected clock period of oscillator. Any frequency informationassociated with the digital phase input is normalized to an externalreference frequency. Further information concerning the phase andfrequency normalization can be found in U.S. Published PatentApplication 2003/0133522, filed May 22, 2002, which is assigned to theassignee of the present application, and the contents of thisapplication are hereby incorporated by reference.

A PM path normalization component 26 adjusts the normalized phase inputfor the current variations in the condition of the system. The result isa digital input that is dependent on any of process, voltage, andtemperature (PVT) variations within the system. The PVT-dependent signalis operative to produce a desired radio frequency (RF) signal at anassociated frequency synthesizer 28 given the present conditions of thesystem. For example, the normalization component 26 can adjust forchanges in the temperature and voltage experienced by the systemcomponents. The frequency synthesizer 28 produces an RF signal accordingto the PVT-dependent digital input. For example, the frequencysynthesizer 28 can comprise a digitally controlled oscillator. Thefrequency synthesizer provides a radio frequency (RF) input signal tothe power amplifier 18.

A second digital input is provided to the amplitude modulated (AM) pathto control the amplitude of the output of the power amplifier 18. Forexample, the second digital input can control a supply voltage for thepower amplifier 18, or can be provided to another component (e.g., aninternal power amplifier) to control the amplitude of the poweramplifier 18 output. The signal is received at a digital predistorter32. The digital predistorter 32 predistorts the digital input to accountfor nonlinear behavior of the power amplifier 18. The distortingbehavior of the predistorter 32 is controlled by one or morepredistortion parameters. These parameters can represent, for example,filter coefficients or values within a look-up table.

The predistorted signal is then provided to a gain normalizationcomponent 34 on the amplitude modulated path. It will be appreciatedthat the digital predistorter 32, and the digital processor 12 alloperate within a normalized domain, such that the inputs and outputs ofthe components are normalized to standard system parameters (e.g., areference voltage or an outermost circle on an I/Q constellation). Thissimplifies the operation and design of these components. The gainnormalization component 34 adjusts the digital input for variations inthe behavior of the power amplifier 18 and components in the amplitudepath due to changes in condition of the system as to convert theamplitude modulated path input from the normalized domain to aPVT-dependent domain. The result is a digital input that can produce adesired amplitude at the power amplifier given the presentcharacteristics of the system. For example, the gain normalizationcomponent 34 can adjust for changes in the temperature and voltageexperienced by the system components. Once the signal has been convertedto the PVT-dependent domain, it is applied to a suitable controlmechanism for the amplitude of the output of the power amplifier 18.

A portion of the power amplifier output is provided to the receiver path16 through a coupling element (not shown). The coupling element cancomprise a coupler that directly provides a portion of the poweramplifier output to the receiver path 16. Alternatively, the couplingelement can comprise the T/R switch 22, with the signal reaching thereceiver path 16 through parasitic leakage through the switch. In thereceiver path 16, the signal is processed to convert the signal into adigital signal that is suitable for digital processing. This process caninclude sampling, downconversion, filtering, and, of course,analog-to-digital conversion of the signal. The digital signal producedby the receiver path 16 is then provided to a signal evaluator 40associated with the digital processor 12. The signal evaluator 40measures the spectral regrowth of the signal as the power of the signalin frequency channels outside of a desired frequency range or channel.Appropriate predistortion parameters for the digital predistorter 32 canbe calculated from the measured signal power to mitigate this spectralregrowth.

FIG. 2 illustrates an exemplary mobile digital transceiver system 100 inaccordance with the present invention. The transceiver system comprisesa digital processor 102, an antenna 104, an external power amplifier106, a transmitter portion 110 and a receiver portion 130. Thetransceiver system 100 can select between a transmit mode and a receivemode at a T/R switch 108 connecting the antenna to the transmitter 110and the receiver 130. It will be appreciated that the digital processor,the transmitter 110 and the receiver 130 can be implemented as anintegrated circuit on a single deep sub-micron CMOS chip.

The transmitter portion 110 receives two digital signals representing adesired output signal from the digital processor. A normalized amplitudeword is provided to an amplitude modulated (AM) path of the transmitter110. A normalized tuning word (NTW) is provided to an AM-PM digitalpredistorter 111 on a phase modulated (PM) path of the transmitter 110.The AM-PM predistorter 111 adjusts the normalized tuning word tomitigate changes in the phase (or delay time) of the power amplifieroutput associated with variations of amplitude within the poweramplifier output. The external power amplifier 106 and variouscomponents within the transceiver (e.g., an internal power amplifier118) can cause a delay within their respective output signals that varywith the amplitude of the signals.

The AM-PM predistorter 111 corrects for this induced delay according tothe expected amplitude of the signal. The expected amplitude can bederived from a normalized amplitude word (NAW) associated with the AMpath of the transmitter 110. For example, the AM-PM predistorter 111 canbe implemented as a look-up table that contains a phase correction foreach amplitude or a digital filter that can be tuned to provide anappropriate delay into the normalized tuning word according to thederived amplitude. Alternatively, the AM-PM predistorter 111 can beimplemented as a parameterized function. It will be appreciated that theAM-PM predistortion does not need to be performed on a normalizeddigital input. For example, the AM-PM predistorter can be locateddownstream of a normalization component (e.g., 114) and receivePVT-dependent phase and amplitude inputs.

The predistorted normalized tuning word is provided to a frequencysynthesizer 112 along a phase modulation path. The frequency synthesizer112 can be implemented using one or more digital phase-locked loops. Thenormalized tuning word represents a desired frequency variation for theoutput signal from a center frequency associated with the system. Withinthe frequency synthesizer 112, the normalized tuning word is received ata digitally controlled oscillator (DCO) gain normalization component114. The DCO gain normalization component 114 converts the normalizedinput from a normalized domain to a PVT-dependent domain, and to providean oscillator tuning word associated with a digitally controlledoscillator 116. For example, the DCO gain normalization component 114can adjust the signal for current variations in the temperature andvoltage of one or more components from standard values.

The digitally-controlled oscillator 116 generates an output with afrequency of oscillation f_(v) that is a physically-inherent function ofthe digital oscillator tuning word (OTW) input. The frequency ofoscillation is generally a nonlinear function of the OTW. However,within a limited range of operation, the action of the digitallycontrolled oscillator 116 can be approximated by a linear transferfunction, such that:

f _(v) =f ₀ +Δf _(v) =f ₀ +K _(DCO) *OTW  Eq. 1

where Δf_(v) is a deviation from a certain center frequency f₀ andK_(DCO) is a gain coefficient.

K_(DCO) can be defined as a frequency deviation Δf_(v) (in Hz) from acertain oscillating frequency f_(v) in response to one least significantbit (LSB) of change in the OTW. Within a linear range of operation,K_(DCO) can also be expressed as:

$\begin{matrix}{K_{DCO} = \frac{\Delta \; {fv}}{\Delta \; {OTW}}} & {{Eq}.\mspace{14mu} 2}\end{matrix}$

-   -   where Δ(OTW) designates a change in the OTW value.

Due to its analog nature, the K_(DCO) gain is subject to process andenvironmental factors which cannot be known precisely, so an estimatethereof, K′_(DCO), must be determined. The estimate K′_(DCO) can becalculated entirely in the digital domain by observing phase errorresponses to the past DCO phase error corrections. The actual DCO gainestimation involves arithmetic operations, such as multiplication ordivision, and averaging, and can be performed, for example, by dedicatedhardware or a digital signal processor (DSP).

The gain normalization component 114 utilizes this estimate to decouplethe phase and frequency information throughout the system from the PVTvariations that normally affect the DCO 116. The phase information isnormalized to a clock period T_(v) of the oscillator, whereas thefrequency information is normalized to the value of an externalreference frequency f_(R). The digital input to the DCO gainnormalization 114 is a fixed-point normalized tuning word (NTW), whoseinteger part LSB corresponds to f_(R). The DCO gain normalization 114applies a multiplier to the predistorted NTW, the normalized domaininput, to obtain the oscillator tuning word (OTW), a PVT-dependentdomain input, such that:

$\begin{matrix}{{OTW} = {{NTW}*\frac{f_{R}/{LSB}}{K_{DCO}^{\prime}}}} & {{Eq}.\mspace{14mu} 3}\end{matrix}$

The oscillator tuning word from the DCO gain normalization component 114is provided to the digitally controlled oscillator 116. The digitallycontrolled oscillator 116 provides a digital-to-frequency conversion toproduce an RF signal having a desired frequency from the oscillatortuning word. The RF signal is a periodic waveform whose frequency is afunction of the normalized tuning word. The digitally controlledoscillator can be implemented as a digital application specificintegrated circuit (ASIC) cell, having digital inputs and outputs. Theoutput of the digitally controlled oscillator 116 is provided to aninternal power amplifier (IPA) 118 as an input signal.

A normalized amplitude word (NAW) is provided from the digital processorto a digital AM-AM predistorter 122 along an amplitude modulation path.The digital AM-AM predistorter 122 applies a predistortion to thenormalized amplitude word to adjust for nonlinear behavior of theexternal power amplifier 106 and the internal power amplifier 118.Conceptually, the nonlinearities introduced to the signal by theexternal power amplifier 106 and the internal power amplifier 118 can berepresented as a transfer function. The AM-AM predistorter 122 applies atransfer function to the normalized amplitude word that is inverse tothe transfer function represented by the power amplifiers 106 and 118.This inverse function is defined by one or more predistortion parametersprovided as control data from the digital processor 102. By way ofexample, the digital AM-AM predistorter 122 can be implemented as adigital filter, with the predistortion parameters comprising filtercoefficients of the digital filter. Alternatively, the digital AM-AMpredistorter can be implemented as a look-up table, with thepredistortion parameters representing values of the look-up table.Furthermore, the digital AM-AM predistorter can be implemented as aparameterized function.

The predistorted signal is then provided to an internal power amplifier(IPA) gain normalization component 124. It will be appreciated that thedigital AM-AM predistorter 122, and the digital processor 102 alloperate within a normalized domain, such that the inputs and outputs ofthe components are normalized to standard system parameters (e.g., areference voltage or the outermost circle on an I/Q constellation). Thissimplifies the operation and design of these components. The IPAnormalization component 124 adjusts the normalized amplitude word forcurrent variations in the behavior of one or more of the external poweramplifier 106, the internal power amplifier 118, and components in theamplitude path due to changes in condition of the system to remove theamplitude modulated path signal from the normalized domain. The resultis an amplitude control word that can produce a desired amplitude at theinternal power amplifier 118 given the present characteristics of thesystem. For example, the IPA normalization component 124 can adjust forchanges in the temperature and voltage experienced by the systemcomponents.

The IPA gain normalization component 124 operates in much the samefashion as the DCO gain normalization device. The exact gain provided bythe power amplifier for a particular input is subject to process andenvironmental factors which cannot be known precisely, so an estimatethereof, K′_(IPA), must be determined. The estimate K′_(IPA) can becalculated entirely in the digital domain by observing responses to pastgain corrections. The actual IPA gain estimation may involve arithmeticoperations, such as multiplication or division and averaging, or anexhaustive or iterative search for an optimal solution and can beperformed, for example, by dedicated hardware or a digital signalprocessor (DSP).

The IPA gain normalization component 124 utilizes this estimate todecouple the amplitude information throughout the system from the PVTvariations that normally affect the internal power amplifier 118. Theamplitude information is normalized to a standardized voltage, V₀. Thedigital input to the IPA gain normalization 124 is a fixed-pointnormalized amplitude word (NAW), whose integer part LSB corresponds toV₀. The IPA gain normalization 124 applies a multiplier to thenormalized amplifier word, the normalized domain input, to obtain theamplifier control word, a PVT-dependent domain input, such that:

$\begin{matrix}{{ACW} = {{NAW}*\frac{V_{0}/{LSB}}{K_{IPA}^{\prime}}}} & {{Eq}.\mspace{14mu} 4}\end{matrix}$

The amplitude control word is provided as a supply input or a digitalword input to the internal power amplifier 118. In the illustratedexample, the internal power amplifier 118 can be implemented as a classE switching amplifier, comprising a series of digital switches and amatching network. A discussion of an exemplary class E switchingamplifier can be found in U.S. Published Patent Application2002/0180547, filed Nov. 22, 2002, which is assigned to the assignee ofthe present application, and the contents of this application are herebyincorporated by reference. The internal power amplifier 118 amplifiesthe RF signal provided by the frequency synthesizer 112 with a supplydetermined by the amplitude control word and provides the amplifiedsignal to the external power amplifier 106. The amplitude of theinternal power amplifier 118 output can be controlled by a digital wordapplied to the series of switches. For example, the internal poweramplifier 118 can be operated at saturation, with the supply dynamicallycontrolled by the amplifier control word. The external power amplifier106 amplifies the received signal using a fixed supply voltage. Theamplified signal can be provided to the antenna 104 for transmission.

A portion of the amplified RF signal can be provided to the receiverportion 130 for analysis via parasitic coupling at the T/R switch 108for calibration of the AM-AM predistorter 122. A signal for calibrationcan also be provided to the receiver 130 through a test multiplexer pin(not shown) or a coupler (not shown) integrated into the integratedtransceiver chip. Calibration can be performed using a signaltransmitted during normal operation of the transmitter or thetransmitter portion 110 can provide a test signal that contains a fullrange of signals for the system. The calibration process can beperformed at the factory, each time the unit is powered, or periodicallyduring the operation of the transceiver. The receiver portion 130 andthe transmitter portion 110 utilize a common local oscillator, so thecarrier signal will have a frequency equal to that of the localoscillator of the receiver 130. Thus, when the signal is demodulated atthe receiver 130, it will contain a strong DC component along withother, less prominent signals within the desired channel. The nonlinearbehavior of the external power amplifier 106 and the internal poweramplifier 118 can cause spectral regrowth, causing the signal to spreadto frequencies outside of the desired frequency range or channel.

The attenuated copy of the signal is provided to a sampling unit 134. Inthe illustrated example, the sampling unit 134 samples the provided RFsignal directly, without the need for prior analog downconverting of thesignal. An exemplary sampling unit for this purpose can be found in U.S.Published Patent Application 2003/0035499, filed Jul. 8, 2002, which isassigned to the assignee of the present application, and the contents ofthis application are hereby incorporated by reference. The output of thesampling unit is provided to an analog-to-digital converter (ADC) 136that converts the sampled signal into a digital signal. In an exemplaryembodiment, the ADC 136 is a sigma-delta ADC that utilizes a sigma-deltamodulator, a comparatively low resolution but high speed ADC, and adecimation filter to achieve high-resolution analog-to-digitalconversion over the frequency band of interest. The output of the ADC136 is fed back to a feedback control unit 138.

The feedback control unit 138 works in conjunction with the samplingunit to measure the DC level at the filter and apply the correctionnecessary to eliminate it. The removal of the DC component allows for amore sensitive measurement of the spectral regrowth within the signal.The corrected signal is provided to a signal evaluation component 140,associated with the digital processor 102. The signal evaluationcomponent 140 measures the spectral regrowth in the signal andcalculates appropriate predistortion parameters to mitigate the measuredspectral regrowth. These parameters are then provided to the digitalAM-AM predistorter 122 as a control input.

FIG. 3 illustrates an exemplary mobile digital transceiver system 200 inaccordance with the present invention. The illustrated system isintended to operate as a pulse amplitude modulation (PAM) system, suchthat information can be carried through the phase and amplitude of thesignal. For example, the system can be utilized as part of an EnhancedData for GSM Evolution (EDGE) modulation scheme. The transceiver systemcomprises a digital processor 202, an antenna 204, an external poweramplifier module 206, a transmitter portion 210 and a receiver portion240. The transceiver system 200 can select between a transmit mode and areceive mode at a T/R switch 208 connecting the antenna to thetransmitter 210 and the receiver 230. It will be appreciated that thedigital processor 202, the transmitter 210 and the receiver 230 can beimplemented on a single deep sub-micron CMOS chip.

The transmitter portion 210 receives two digital signals representing adesired output signal from the digital processor. A normalized amplitudeword is provided to an amplitude modulated (AM) path of the transmitter210. A normalized tuning word (NTW) is provided to an AM-PM digitalpredistorter 211 on a phase modulated (PM) path of the transmitter 210.The AM-PM predistorter 211 adjusts the normalized tuning word tomitigate changes in, the phase (or delay time) of the power amplifieroutput associated with variations of amplitude within the poweramplifier output. The external power amplifier 206 and variouscomponents within the transceiver (e.g., an internal power amplifier218) can cause a delay within their respective output signals that varywith the amplitude of the signals.

The AM-PM predistorter 211 corrects for this induced delay according tothe expected amplitude of the signal. The expected amplitude can bederived from a normalized amplitude word (NAW) associated with the AMpath of the transmitter 210. For example, the AM-PM predistorter 211 canbe implemented as a look-up table that contains a phase correction foreach amplitude or a digital filter that can be tuned to provide anappropriate delay into the normalized tuning word according to thederived amplitude. It will be appreciated that the AM-PM predistortiondoes not need to be performed on a normalized digital input. Forexample, the AM-PM predistorter can be located downstream of anormalization component (e.g., 214) and receive PVT-dependent phase andamplitude inputs.

The predistorted normalized tuning word is provided to a frequencysynthesizer 212 along a phase modulation path. The frequency synthesizer212 can be implemented using one or more digital phase-locked loops. Thenormalized tuning word represents a desired frequency variation for theoutput signal from a center frequency associated with the system. Withinthe frequency synthesizer 212, the normalized tuning word is received ata digitally controlled oscillator (DCO) gain normalization component214. The DCO gain normalization component 214 calibrates the normalizedtuning word such that the input provided to a digitally controlledoscillator 216 is properly adjusted for PVT variations of the system.

The digitally-controlled oscillator (DCO) 216 generates an output with afrequency of oscillation f_(v) that is a physically-inherent function ofthe digital oscillator tuning word (OTW) input. The frequency ofoscillation is generally a nonlinear function of the OTW. However,within a limited range of operation, the action of the digitallycontrolled oscillator 216 can be approximated by a linear transferfunction, such that:

f _(v) =f ₀ +Δf _(v) =f ₀ +K _(DCO) *OTW  Eq. 5

where Δf_(v) is a deviation from a certain center frequency f₀ andK_(DCO) is a gain coefficient.

K_(DCO) can be defined as a frequency deviation Δf_(v) (in Hz) from acertain oscillating frequency f_(v) in response to one least significantbit (LSB) of change in the OTW. Within a linear range of operation,K_(DCO) can also be expressed as:

$\begin{matrix}{K_{DCO} = \frac{\Delta \; {fv}}{\Delta \; {OTW}}} & {{Eq}.\mspace{14mu} 6}\end{matrix}$

-   -   where Δ(OTW) designates a change in the OTW value.

Due to its analog nature, the K_(DCO) gain is subject to process andenvironmental factors which cannot be known precisely, so an estimatethereof, K′_(DCO), must be determined. The estimate K′_(DCO) can becalculated entirely in the digital domain by observing phase errorresponses to the past DCO phase error corrections. The actual DCO gainestimation involves arithmetic operations, such as multiplication ordivision, and averaging, and can be performed, for example, by dedicatedhardware or a digital signal processor (DSP).

The gain normalization component 214 utilizes this estimate to decouplethe phase and frequency information throughout the system from the PVTvariations that normally affect the DCO 216. The phase information isnormalized to a clock period T_(v) of the oscillator, whereas thefrequency information is normalized to the value of an externalreference frequency f_(R). The digital input to the DCO gainnormalization 214 is a fixed-point normalized tuning word (NTW), whoseinteger part LSB corresponds to f_(R). The DCO gain normalization 214applies a multiplier to the predistorted NTW, the normalized domaininput, to obtain the oscillator tuning word (OTW), a PVT-dependentdomain input, such that:

$\begin{matrix}{{OTW} = {{NTW}*\frac{f_{R}/{LSB}}{K_{DCO}^{\prime}}}} & {{Eq}.\mspace{14mu} 7}\end{matrix}$

The oscillator tuning word from the DCO gain normalization component 214is provided to the digitally controlled oscillator 216. The digitallycontrolled oscillator 216 provides a digital-to-frequency conversion toproduce an RF signal having a desired frequency from the tuning word.The RF signal is a periodic waveform whose frequency is a function ofthe normalized tuning word. The digitally controlled oscillator can beimplemented as a digital application specific integrated circuit (ASIC)cell, having digital inputs and outputs. The output of the digitallycontrolled oscillator 216 is provided to an internal power amplifier(IPA) 218 as an input signal. The internal power amplifier 218 amplifiesthe signal according to a fixed digital input to its supply terminal toproduce a constant envelope RF signal. The RF signal is provided as aninput signal to the external power amplifier 206.

A normalized amplitude word (NAW) is provided from the digital processorto a digital AM-AM predistorter 222 along an amplitude modulation path.The digital AM-AM predistorter 222 applies a predistortion to thenormalized amplitude word to adjust for nonlinear behavior of theexternal power amplifier 206 and the internal power amplifier 218.Conceptually, the nonlinearities introduced to the signal by the poweramplifiers 206 and 218 can be represented as a transfer function. Thepredistorter 222 applies a transfer function to the normalized tuningword that is inverse to the transfer function represented by the poweramplifiers 206 and 218. This inverse function is defined by one or morepredistortion parameters provided as control data from the digitalprocessor 202. By way of example, the digital AM-AM predistorter 222 canbe implemented as a digital filter, with the predistortion parameterscomprising filter coefficients of the digital filter. Alternatively, thedigital AM-AM predistorter can be implemented as a look-up table, withthe predistortion parameters representing values of the look-up table.Furthermore, the digital AM-AM predistorter can be implemented as aparameterized function.

The predistorted signal is then provided to a power amplifier (PA) gainnormalization component 224. It will be appreciated that the digitalAM-AM predistorter 222, and the digital processor 202 all operate withina normalized domain, such that the inputs and outputs of the componentsare normalized to standard system parameters (e.g., a referencevoltage). This simplifies the operation and design of these components.The PA normalization component 224 adjusts the normalized amplitude wordfor current variations in the behavior of the external power amplifier206 and/or other components in the amplitude path due to changes incondition of the system. This effectively converts the signal from thenormalized domain to a PVT-dependent domain. The result is an amplitudecontrol word that that can produce a power amplifier output having adesired amplitude given the present characteristics of the system. Forexample, the PA normalization component 224 can adjust for changes inthe temperature and voltage experienced by the power amplifier.

The PA gain normalization component 224 operates in much the samefashion as the DCO gain normalization device. The exact gain provided bythe power amplifier for a particular input is subject to process andenvironmental factors which cannot be known precisely, so an estimatethereof, K′_(PA), must be determined. The estimate K′_(PA) can becalculated entirely in the digital domain by observing responses to thepast gain error corrections. The actual PA gain estimation may involvearithmetic operations, such as multiplication or division and averaging,or an exhaustive or iterative search for optimal values, and can beperformed, for example, by dedicated hardware or a digital signalprocessor (DSP).

The gain normalization component 224 utilizes this estimate to decouplethe amplitude information throughout the system from the PVT variationsthat normally affect the external power amplifier 206. The amplitudeinformation is normalized to a standardized voltage, V₀. The digitalinput to the PA gain normalization 224 is a fixed-point normalizedamplitude word (NAW), whose integer part LSB corresponds to V₀. The PAgain normalization 224 applies a multiplier to the normalized amplitudeword (NAW), the normalized domain input, to obtain the amplitude controlword (ACW), a PVT-dependent domain input, such that:

$\begin{matrix}{{ACW} = {{NAW}*\frac{V_{0}/{LSB}}{K_{PA}^{\prime}}}} & {{Eq}.\mspace{14mu} 8}\end{matrix}$

The amplitude control word is provided to a digital-to-analog converter(DAC) 226. The DAC 226 converts the amplitude control word into ananalog control signal. In an exemplary embodiment, the DAC 226 can be aflash DAC or a sigma-delta DAC that utilizes a sigma-delta modulator, acomparatively low resolution but high-speed DAC, and a low-pass filterto achieve high-resolution analog-to-digital conversion over thefrequency band of interest. The analog control signal is provided to asupply input of the external power amplifier 206.

The external power amplifier module 206 comprises a comparator 230, alinear MOS transistor 232, and a voltage source, V_(BATT). The MOStransistor is driven by the comparator 230, such that the transistor 232permits the voltage source to provide a regulated drain current to asupply of an amplifier component 233 while the comparator 230 provides anegative feedback to regulate the drain current. A primary input of thecomparator is provided by the output of the DAC 226, while a comparisoninput is provided as a feedback from the supply input. Accordingly, theanalog control signal controls the drain current provided to the supplyinput, and thus the amplitude of the output the external power amplifier206 when the power amplifier is operated in a saturation mode. Theexternal power amplifier 206 thus amplifies the constant envelope RFsignal from the internal power amplifier 218 according to the providedsupply voltage. The amplifier 206 output can be provided to the antenna204 for transmission.

In an exemplary implementation, the system 200 can be utilized for apulse amplitude modulation (PAM) scheme, a code division multiple access(CDMA) scheme, a time division multiple access (TDMA) scheme and afrequency modulation scheme, such as Global System for MobileCommunications (GSM) or Bluetooth. For example, the system couldalternate between an EDGE modulation scheme and a GSM modulationarrangement. When the system is operating as a frequency modulation(e.g., Bluetooth or GSM) system, it assumes a saturation mode, where theexternal power amplifier module 206 is maintained at a saturation levelfor maximum efficiency. When the system is performing PAM, the systemcan enter a linear mode where the voltage supply to the power amplifieris backed off to an appropriate level. The system can be switchedbetween the two modes by altering the amplitude supply word to adjustthe supply provided to the external power amplifier 206.

A portion of the amplified RF signal can be provided to the receiverportion 230 for analysis via parasitic coupling at the T/R switch 208for calibration of the AM-AM predistorter 222. A signal for calibrationcan also be provided to the receiver 230 through a test multiplexer pin(not shown) or a coupler (not shown) integrated into the integratedtransceiver chip. Calibration can be performed using a signaltransmitted during normal operation of the transmitter or thetransmitter portion 210 can provide a test signal that contains a fullrange of signals for the system. The calibration process can beperformed at the factory, each time the unit is powered, or periodicallyduring the operation of the transceiver. The receiver portion 230 andthe transmitter portion 210 utilize a common local oscillator, so thesignal will have a frequency equal to that of the reference frequency ofthe receiver 230. Thus, when the signal is demodulated at the receiver230, it will contain a strong DC component along with other, lessprominent signals within the desired channel. The nonlinear behavior ofthe external power amplifier 206 and the internal power amplifier 218signal can cause spectral regrowth, causing the signal to spread tofrequencies outside of the desired frequency range.

The attenuated copy of the attenuated signal is provided to a samplingunit 234. In the illustrated example, the sampling unit 234 samples theprovided RF signal directly, without the need for prior analogdownconverting of the signal. The output of the sampling unit isprovided to an analog-to-digital converter (ADC) 236 that converts thesampled signal into a digital signal. In an exemplary embodiment, theADC 236 can be a sigma-delta ADC that utilizes a sigma-delta modulator,a comparatively low resolution but high speed ADC, and a decimationfilter to achieve high-resolution analog-to-digital conversion over thefrequency band of interest. The output of the ADC 236 is fed back to afeedback control unit 238.

The feedback control unit 238 works in conjunction with the samplingunit to measure the DC level at the filter and apply the correctionnecessary to eliminate it. The removal of the DC component allows for amore sensitive measurement of the spectral regrowth within the signal.The corrected signal is provided to a signal evaluation component 240,associated with the digital processor 202. The signal evaluationcomponent 240 measures the spectral regrowth in the signal andcalculates appropriate predistortion parameters to mitigate the measuredspectral regrowth. These parameters are then provided to the digitalAM-AM predistorter 222 as a control input.

In view of the foregoing structural and functional features describedabove, certain methods will be better appreciated with reference to FIG.4. It is to be understood and appreciated that the illustrated actions,in other embodiments, may occur in different orders and/or concurrentlywith other actions. Moreover, not all illustrated features may berequired to implement a method. It is to be further understood that thefollowing methodology can be implemented in hardware (e.g., as one ormore integrated circuits or circuit boards containing a plurality ofmicroprocessors), software (e.g., as executable instructions running onone or more processors), or any combination thereof.

FIG. 4 illustrates a methodology 300 for calibrating a digitalpredistorter associated with a digital transceiver. The methodology 300begins at 302, where a digital processor generates a normalizedamplitude input and a normalized phase input representing a desiredsignal. For example, the normalized inputs can be control words for oneor more digital components in the transceiver operated in a normalizeddomain. At 304, the normalized phase and amplitude inputs arepredistorted to mitigate the effects of nonlinear behavior associatedwith a power amplifier. This predistortion can be represented by atransfer function defined by one or more predistortion parameters.

At 306, the normalized inputs are converted from a normalized domain toa PVT-dependent domain to account for PVT deviations in the system froman expected standard. For example, the inputs can be adjusted forchanges in the temperature or voltage of one or more system components.At 308, the PVT-dependent inputs are used to generate a desired RFsignal for the system. For example, the phase modulated input cancontrol a digital frequency synthesizer to provide RF output. Similarly,the amplitude modulated output can control the supply of a poweramplifier to control the amplitude of the amplifier output.

At 310, at least a portion of the RF signal is provided to a receiverpath of the digital transceiver. At 312, the RF output is sampled toprovide a series of discrete time signals. It will be appreciated thatthe signal can be amplified, filtered, and/or downconverted prior tosampling. At 314, the signal is conditioned for analysis. For example,in one embodiment, a DC offset is provided to the signal to mitigate astrong in-channel DC component of the signal. The specifics of theconditioning will depend upon the characteristics of the signal.

At 316, the signal is converted into a digital signal. In an exemplaryembodiment, this can be accomplished via a sigma-delta modulator, a lowresolution analog-to-digital converter, and a decimation filter. At 318,the signal is analyzed at the digital processor. The digital processordetermines the amount of spectral regrowth (e.g., signal power outsideof a desired frequency range or channel) and determines appropriatepredistortion parameters to mitigate the spectral regrowth. For example,the parameters can be calculated or optimal parameters can be derived aspart of an iterative or exhaustive search. The determined predistortionparameters can be provided to a predistortion component in the system ascontrol input.

What has been described above includes examples and implementations ofthe present invention. Because it is not possible to describe everyconceivable combination of components, circuitry or methodologies forpurposes of describing the present invention, one of ordinary skill inthe art will recognize that many further combinations and permutationsof the present invention are possible. Accordingly, the presentinvention is intended to embrace all such alterations, modifications andvariations that fall within the spirit and scope of the appended claims.

1. An integrated transceiver circuit, comprising: a digital polartransmitter path that provides an amplitude/phase signal from a digitalinput, the transmitter path including at least one digital predistorterthat predistorts the digital input to mitigate nonlinearities associatedwith a power amplifier; a receiver path associated with the digitaltransmitter path; a coupling element that provides the signal from thetransmitter path to the receiver path; and a signal evaluator thatdetermines values for at least one parameter associated with the digitalpredistorter based on the signal. 2-11. (canceled)
 12. The circuit ofclaim 1, the power amplifier comprising an external power amplifier thatis external to the integrated transceiver circuit.
 13. The circuit ofclaim 12, the power amplifier further comprising an internal poweramplifier, the output of the internal power amplifier being provided tothe external power amplifier.
 14. The circuit of claim 12, the digitaltransmitter path comprising an amplitude modulated path that controlsthe supply to the external amplifier according to a first digital input,and a phase modulated path that provides a radio frequency input to theexternal power amplifier according to a second digital input.
 15. Thecircuit of claim 14, the phase modulated path comprising a digitallycontrolled oscillator.
 16. (canceled)
 17. The circuit of claim 14, thephase modulated path comprising a digital predistorter that adjusts thesecond digital input to mitigate nonlinearities associated with thepower amplifier.
 18. The circuit of claim 14, the amplitude modulatedpath comprising a digital predistorter that adjusts the first digitalinput to mitigate nonlinearities associated with the power amplifier.19-20. (canceled)
 21. A method of calibrating a predistortion componentin a transceiver system, comprising: providing a first digital signal,containing amplitude information related to a desired analog signal, toa transmitter path; providing a second digital signal, containing phaseinformation related to the desired analog signal, to the transmitterpath; predistorting at least one of the first digital signal and thesecond digital signal in the digital domain according to at least onepredistortion parameter; generating an analog signal from the firstdigital signal and the second digital signal; and processing the analogsignal at a receiver path associated with the transmitter path todetermine values for the at least one predistortion parameter. 22-26.(canceled)
 27. The method of claim 21, wherein the receiver pathcomprises a history capacitor coupled to a rotating capacitor.